The invention is related to a digital-to-analog converter having an R-2R-ladder network which is controlled by a plurality of control circuits each associated with one digit of a digital input signal.
For use with digital-to-analog converters R-2R-ladder networks are known which are designed such that all series resistors and terminator resistors at both ends are of the same resistance value R whereas the remaining cross resistors have a doubled resistance value 2R. One end of such an R-2R-ladder network forms an output for delivering an analog signal corresponding to the digital input signal. The digital input signal is composed of a plurality of digits which may be grouped by n+m+1 bit. This signal is converted into an analog signal according to a non-linear segmented characteristic composed of 2.sup.m+1 linear segments each having 2.sup.n amplitude steps. This characteristic is achieved by design of R-2R-ladder network such that in a group of n nodes each connecting a series resistor and an associated cross resistor each node is selectively supplied with a constant current from a respective one of n constant current sources dependent upon the state of a respective one of the n least significant digits of the digital input signal. A node viewed towards the analog signal output has a distance from this ladder network end according to 1 through 2.sup.m-1 nodes determined by the order m of the associated digit. Viewed in the direction of the mentioned end of the R-2R-ladder network the node connecting a cross resistor and a series resistor is supplied with a constant current of a separate constant current source in case that at least one of the m digits of the digital input signal is comprising a binary "1".
There is also known a somewhat different design of such an R-2R-ladder network which has been published in "1978 IEEE International Solid-State Circuits Conference, Digest of Technical Papers", pages 186-187, FIG. 2 above. This R-2R-ladder network also is composed of series resistors having a resistance value R and of cross resistors having a resistance value 2R. One end of the network comprises the analog signal output. The opposite end is terminated by an additional resistor having the resistance value 2R. The number of nodes of this ladder network corresponds to the number of digits of the digital signal to be converted. Binary voltages are to be fed to the connectors of the cross resistors which are opposite to the series resistors whereby the binary voltages correspond to the digits of the digital signal.
The resistors of the R-2R-ladder network can be implemented by correspondingly controlled MOS transistors. MOS transistors forming the series resistors of resistance value R are controlled to be constantly conductive. Cross resistors are composed of source-drain-paths of two MOS transistors or two MOS transistor pairs. Each single MOS transistor when used as a cross resistor has the resistance value 2R in its conductive state. If a cross resistor is composed of a pair of MOS transistors arranged in series, each transistor has the resistance value R when conductive. Each of the MOS transistors forming the cross resistors of one ladder cell are commonly connected by one main electrode to the source of the associated MOS transistors designed as series resistor of the cell. Corresponding first transistors of the transistor pairs each coupled to a respective series transistor are commonly connected to ground by their second main electrodes whereas the second MOS transistors correspondingly are commonly connected to a control potential. Associated with each of the MOS transistors forming a cross-resistor is a respective one of control circuits having two alternatively activated outputs each connected to a gate of a first or second MOS transistor respectively.
The accuracy of converting a digital input signal into an analog output signal apart from geometrical tolerances of the MOS transistors comprising the R-2R-ladder network depends upon the influence of the gate-source voltage and the gate-drain-voltage on the effective resistance of a conductive MOS transistor. Therefore, resistance values of the individual MOS transistors deviate from a theoretically uniform resistance value R in both directions relatively more or less. The actual amount of relative deviation is subject to the present bit combination of the digital input signal. The resulting converted analog signal may present a relative failure of up to 20%.
In "1978 IEEE International Solid-State Circuit Conference, Digest of Technical Papers", pages 186 and 187, FIG. 2 below, furthermore, there is shown another design of an R-2R-ladder network also composed of series resistors of resistance values R and cross resistance values 2R. To a constant current is supplied to the node connecting a cross resistor and a neighboring series resistor and forming one end of the R-2R ladder network. The opposite end of the R-2R-ladder network is terminated by an additional resistor of resistance value 2R. Again, the number of cross resistors of the ladder network corresponds to the number of digits of the digital signal. The connectors of the cross resistors opposite to the node connection are, dependent upon the present bit combination of the digital signal, directly connectable either to the low end pole of the constant current source or to a sum current line. The sum current line supplies identical potentials to all connectors and represents the analog signal output.
Also in this case the resistors of the R-2R-ladder network may be implemented by MOS transistors, wherein all resistors of resistance value 2R may be composed of a pair of two identical MOS transistors connected in series and having a resistance value R when conductive. Cross resistors are implemented by a first and a second pair of MOS transistors. All first transistor pairs are inserted between a respective node connecting a series resistor to a cross resistor and the grounded low end of the constant current source. The second transistor pairs are arranged between such a respective node and the sum current line.
By an R-2R-ladder network of this design theoretically an accurate digital-to-analog conversion is achieved. This is true if the resistance values R of the individual MOS transistors in actual implementation can be obtained such that just negligible deviation from the uniform value can occur. In practice, the accuracy of the operation of the network again depends upon geometrical tolerances of the MOS transistors and the influence of gate-source-voltages and gate-drain-voltages on the effective resistances of MOS transistors when conductive.
It is, therefore, an object of the present invention to provide an improved digital-to-analog converter composed of an R-2R-ladder network wherein the resistors of the network are implemented by MOS transistors.
Another object of the present invention is to provide such a digital-to-analog converter of a design which allows to match the theoretically uniform resistance value of the R-2R-ladder network in fact more precisely than with conventional cells of R-2R-ladder networks.
Still another object of the present invention is to compose the R-2R-ladder network of less MOS transistors for obtaining an advanced design in an integrated semiconductor technology.